The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of the growth, functional density of the semiconductor devices has increased with the decrease of device feature size or geometry. The scaling down process generally provides benefits by increasing production efficiency, reducing costs, and/or improving device performance, but on the other hand increases complexity of the IC manufacturing processes.
In the IC manufacturing processes, deposition processes are widely used on varying surface topologies in both front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) process. In FEOL process, deposition processes may be used to form polysilicon material on a substantially flat substrate, and deposition processes may be used to form metal interconnect layers within a cavity in a dielectric layer in BEOL processing. However, problems exist from the quality of the deposited material, and further improvements to the deposition processes are constantly necessary to satisfy the performance requirement in the scaling down process.